#include "sal.h"
#include "ctc_cli.h"
#include "usw/include/drv_enum.h"
#include "drv_api.h"
#include "usw/include/drv_common.h"
#include "usw/include/drv_chip_ctrl.h"
#include "ctc_dkit.h"
#include "ctc_dkit_common.h"
#include "ctc_usw_dkit.h"
#include "ctc_usw_dkit_interface.h"
#include "ctc_at_dkit_serdes.h"

extern ctc_dkit_chip_api_t* g_dkit_chip_api[CTC_DKITS_MAX_LOCAL_CHIP_NUM];
extern ctc_dkit_master_t* g_usw_dkit_master[CTC_DKITS_MAX_LOCAL_CHIP_NUM];

#define CTC_DKIT_PER_DP_CHANNEL_NUM                   26
#define CTC_DKIT_DP_MAX_NUM                           2
#define CTC_DKIT_QOS_QUEUE_NUM_PER_CHAN               12
#define CTC_DKIT_ENQ_MODEL_QUEUE_NUM                  18
#define CTC_DKIT_PER_CHAN_UC_QUEUE_NUM                12
#define CTC_DKIT_PER_CHAN_MC_QUEUE_NUM                6
#define CTC_DKIT_REASON_TOTAL_QUEUE_NUM               128
#define CTC_DKIT_REASON_TOTAL_QUEUE_NUM_UC            32
#define CTC_DKIT_CPU_REASON_GRP_NUM_EUNIT             4
#define CTC_DKIT_CPU_REASON_GRP_Q_NUM_EUNIT           32
#define CTC_DKIT_CHANID_EUNIT0                        466
#define CTC_DKIT_CHANID_DMA_RX0                       486
#define CTC_DKIT_DMA_SUB_CHAN                         24

#define CTC_DKIT_IS_BASIC_QUEUE(queue_id) ((queue_id) < g_usw_dkit_master[lchip]->base_queue_excp)
#define CTC_DKIT_GET_DP_ID_BY_QUEUE_ID(que_id) (CTC_DKIT_IS_BASIC_QUEUE(que_id) ? (((((que_id)) / CTC_DKIT_QOS_QUEUE_NUM_PER_CHAN) / CTC_DKIT_PER_DP_CHANNEL_NUM) & 0x1) : 0)
#define CTC_DKIT_GET_PP_ID_BY_QUEUE_ID(que_id) (CTC_DKIT_IS_BASIC_QUEUE(que_id) ? \
                                                 (((((que_id)) / CTC_DKIT_QOS_QUEUE_NUM_PER_CHAN) / CTC_DKIT_PER_DP_CHANNEL_NUM) >> 1) : \
                                                 (CTC_DKIT_IS_EUNIT_QUEUE(que_id) ? (CTC_DKIT_MAP_EUNIT_QUEUE(que_id)/CTC_DKIT_CPU_REASON_GRP_Q_NUM_EUNIT/2 + 1): 0))


#define CTC_DKIT_IS_EUNIT_QUEUE(queue_id) ((queue_id) >= g_usw_dkit_master[lchip]->queue_base_eunit && (queue_id) < g_usw_dkit_master[lchip]->queue_num)
#define CTC_DKIT_IS_DMA_QUEUE(queue_id) ((queue_id) >= g_usw_dkit_master[lchip]->base_queue_excp && (queue_id) < (g_usw_dkit_master[lchip]->base_queue_excp + CTC_DKIT_REASON_TOTAL_QUEUE_NUM + CTC_DKIT_REASON_TOTAL_QUEUE_NUM_UC))
#define CTC_DKIT_MAP_EUNIT_QUEUE(queue_id) ((queue_id) - g_usw_dkit_master[lchip]->queue_base_eunit)

#define CTC_DKIT_GET_CHAN_INFO(que_id, dp_chan, pp_id, dp_id)                        \
    {                                                                               \
        uint16 __tmp_chan = ((que_id)) / CTC_DKIT_QOS_QUEUE_NUM_PER_CHAN; \
        if (CTC_DKIT_IS_BASIC_QUEUE(que_id))                                      \
        {                                                                           \
            dp_chan = __tmp_chan % CTC_DKIT_PER_DP_CHANNEL_NUM;           \
            __tmp_chan /= CTC_DKIT_PER_DP_CHANNEL_NUM;                    \
            pp_id = __tmp_chan >> 1;                                                \
            dp_id = __tmp_chan & 0x1;                                               \
        }                                                                           \
        else                                                                        \
        {                                                                           \
            dp_chan = CTC_DKIT_DMA_SUB_CHAN;                                             \
            dp_id = CTC_DKIT_GET_DP_ID_BY_QUEUE_ID(que_id);                          \
            pp_id = CTC_DKIT_GET_PP_ID_BY_QUEUE_ID(que_id);                          \
        }                                                                           \
    }

#define CTC_DKIT_VCHIP_DUAL_CORE_LCHIP_MAP(lchip, dual_core_lchip) { \
            uint8 _core_pp_num = drv_vchip_get_pp_num(lchip) / 2; \
            uint8 _pp_id = (lchip) - drv_vchip_get_pp_base(lchip); \
            dual_core_lchip = (_pp_id >= _core_pp_num) ? ((lchip) - _core_pp_num) : ((lchip) + _core_pp_num); \
    }

#define CTC_DKIT_CHAN_TO_DP_ID(subchanId) (((subchanId) >> 5) & 0x1)
#define CTC_DKIT_CHAN_TO_PP_ID(subchanId) (((subchanId) >> 6) & 0x7)
#define CTC_DKIT_SUB_CHAN_MASK 0x1F
#define CTC_DKIT_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))

STATIC uint32
_ctc_at_dkit_get_channel_by_gport(uint8 lchip, uint16 gport, uint8 is_rx)
{
    uint16 local_phy_port = 0;
    uint32 channel = 0xFFFFFFFF;
    uint16 i = 0;
    uint32 cmd = 0;
    uint32 value = 0;

    local_phy_port = gport;
    for (i = 0; i < CTC_DKIT_ONE_SLICE_CHANNEL_NUM; i++)
    {
        cmd = is_rx ? DRV_IOR(IpeHeaderAdjustPhyPortMap_t, IpeHeaderAdjustPhyPortMap_localPhyPort_f) : DRV_IOR(EpeHeaderAdjustPhyPortMap_t, EpeHeaderAdjustPhyPortMap_localPhyPort_f);
        DRV_FIELD_IOCTL(lchip, i, cmd, &value);
        if (value == local_phy_port)
        {
            channel = i;
            break;
        }
    }

    return channel;
}

int32
ctc_at_dkit_device_info(void* p_para)
{
    /* get info by show datapath status  */
    return CLI_SUCCESS;
}

int32
ctc_at_dkit_get_get_channel_by_queue_id(uint8 lchip, uint16 queue_id)
{
    EpeHeaderAdjustChannelPortMap_m ChannelPortMap;
    uint32 cmd = 0;
    uint8 dp_chan = 0;
    uint8 pp_id = 0;
    uint8 dp_id = 0;
    uint32 channel = 0;

    if (CTC_DKIT_IS_EUNIT_QUEUE(queue_id))
    {
        /*to ecpu*/
        channel = CTC_DKIT_CHANID_EUNIT0 + CTC_DKIT_MAP_EUNIT_QUEUE(queue_id) / CTC_DKIT_CPU_REASON_GRP_Q_NUM_EUNIT;
    }
    else if (CTC_DKIT_IS_DMA_QUEUE(queue_id))
    {
        channel = CTC_DKIT_CHANID_DMA_RX0;
    }
    else
    {
        CTC_DKIT_GET_CHAN_INFO(queue_id, dp_chan, pp_id, dp_id);
        lchip = drv_vchip_get_pp_base(lchip) + (pp_id);
        cmd = DRV_IOR(EpeHeaderAdjustChannelPortMap_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, dp_chan & 0x1F, DRV_CMD_PP_EN(cmd), &ChannelPortMap);
        channel = GetEpeHeaderAdjustChannelPortMap(V, g_0_ppDestPort_f + (dp_id & 0x1), &ChannelPortMap);
    }

    return channel;
}



STATIC int32
_ctc_at_dkit_get_sub_channel_by_channel(uint8 lchip, uint16 chan, uint16 *sub_chan)
{
    uint32 cmd = 0;
    UcQWritePortChannelMap_m uc_chan_map;

    cmd = DRV_IOR(UcQWritePortChannelMap_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(drv_vchip_get_pp_base(lchip), chan, cmd, &uc_chan_map);
    *sub_chan = GetUcQWritePortChannelMap(V, g_0_channelId_f, &uc_chan_map);

    return CLI_SUCCESS;
}

STATIC int32
_ctc_at_get_channel_by_sub_channel(uint8 lchip, uint8 sub_chan, uint8 dp_id, uint16 *chan)
{
    uint32 cmd = 0;
    EpeHeaderAdjustChannelPortMap_m ChannelPortMap;

    cmd = DRV_IOR(EpeHeaderAdjustChannelPortMap_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, sub_chan & 0x1F, DRV_CMD_PP_EN(cmd), &ChannelPortMap);
    *chan = GetEpeHeaderAdjustChannelPortMap(V, g_0_ppDestPort_f + (dp_id & 0x1), &ChannelPortMap);
    return CLI_SUCCESS;
}

STATIC int32
_ctc_at_dkit_get_q_depth_igr_detail_port_tc(uint8 lchip, uint16 channel, sal_file_t p_wf, bool is_uc)
{
    uint8 i = 0;
    char desc[16] = {0};
    uint32 depth = 0 ;
    uint32 cmd = 0;
    uint32 port_tc_thrd = 0;
    uint16 sub_chan_id = 0;
    uint8 pp_id = 0;
    uint8 dp_id = 0;
    uint32 tbl_cnt_id = 0;
    uint32 field_cnt_id = 0;
    uint32 tbl_thd_id = 0;
    uint32 field_thd_id = 0;

    tbl_cnt_id = (is_uc? DsIrmPortTcCntUc_t: DsIrmPortTcCntMc_t);
    field_cnt_id = (is_uc? DsIrmPortTcCntUc_portTcCnt_f: DsIrmPortTcCntMc_portTcCnt_f);
    tbl_thd_id = (is_uc? DsIrmPortTcLimitedThrdProfileUc_t: DsIrmPortTcLimitedThrdProfileMc_t);
    field_thd_id = (is_uc? DsIrmPortTcLimitedThrdProfileUc_g_0_portTcLimitedThrd_f: DsIrmPortTcLimitedThrdProfileMc_g_0_portTcLimitedThrd_f);
    CTC_DKITS_PRINT_FILE(p_wf, "\n--------------------------------------\n");
    CTC_DKITS_PRINT_FILE(p_wf, "%-10s%-10s%-10s%-10s\n", "SrcCore", "TC",  "Depth", "Thrd");
    CTC_DKITS_PRINT_FILE(p_wf, "--------------------------------------\n");
    _ctc_at_dkit_get_sub_channel_by_channel(lchip, channel, &sub_chan_id);
    dp_id = CTC_DKIT_CHAN_TO_DP_ID(sub_chan_id);
    pp_id = CTC_DKIT_CHAN_TO_PP_ID(sub_chan_id);
    sub_chan_id &= CTC_DKIT_SUB_CHAN_MASK;
    lchip = drv_vchip_get_pp_base(lchip) + (pp_id);
    for (i = 0; i < 8; i++)
    {
        cmd = DRV_IOR(tbl_cnt_id, field_cnt_id);
        DRV_FIELD_IOCTL(lchip, ((sub_chan_id << 3) + i), DRV_CMD_DP_EN(cmd, dp_id), &depth);
        cmd = DRV_IOR(tbl_thd_id, field_thd_id);
        DRV_FIELD_IOCTL(lchip, ((sub_chan_id << 3) + i), DRV_CMD_DP_EN(cmd, dp_id), &port_tc_thrd);

        sal_sprintf(desc, "TC%d", i);
        CTC_DKITS_PRINT_FILE(p_wf, "%-10d%-10s%-10d%-10d\n", pp_id/4, desc, depth, port_tc_thrd << 3);
    }

    return CLI_SUCCESS;
}


STATIC int32
_ctc_at_dkit_get_q_depth_igr_summary(uint8 lchip, sal_file_t p_wf, bool is_uc)
{
    uint32 cmd = 0;
    uint8 i = 0;
    char desc[16] = {0};
    uint32 rt_packet_cnt = 0;
    uint32 c2c_packet_cnt = 0;
    uint32 critical_packet_cnt = 0;
    uint32 igr_total_cnt = 0;
    uint32 rt_packet_thrd = 0;
    uint32 c2c_packet_thrd = 0;
    uint32 critical_packet_thrd = 0;
    uint32 igr_total_thrd = 0;
    uint32 sc_packet_cnt = 0;
    uint32 sc_packet_thrd = 0;
    uint32 tbl_cnt_id = 0;
    uint32 field_cnt_id = 0;
    uint32 tbl_thd_id = 0;
    uint32 field_thd_id = 0;
    ds_t ds={0};

    if (is_uc)
    {
        cmd = DRV_IOR( DsIrmMiscCntUc_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), ds);
        GetDsIrmMiscCntUc(A, c2cCnt_f, ds, &c2c_packet_cnt);
        GetDsIrmMiscCntUc(A, criticalCnt_f, ds, &critical_packet_cnt);
        GetDsIrmMiscCntUc(A, totalCnt_f, ds, &igr_total_cnt);
        cmd = DRV_IOR(DsIrmMiscThrdUc_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), ds);
        GetDsIrmMiscThrdUc(A, c2cThrd_f, ds, &c2c_packet_thrd);
        GetDsIrmMiscThrdUc(A, criticalThrd_f, ds, &critical_packet_thrd);
        GetDsIrmMiscThrdUc(A, totalThrd_f, ds, &igr_total_thrd);
        tbl_cnt_id =DsIrmScCntUc_t;
        field_cnt_id = DsIrmScCntUc_g_0_scCnt_f;
        tbl_thd_id = DsIrmScThrdUc_t;
        field_thd_id = DsIrmScThrdUc_g_0_scThrd_f;
    }
    else
    {
        cmd = DRV_IOR(DsIrmMiscCntMc_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), ds);
        GetDsIrmMiscCntMc(A, c2cCnt_f, ds, &c2c_packet_cnt);
        GetDsIrmMiscCntMc(A, criticalCnt_f, ds, &critical_packet_cnt);
        GetDsIrmMiscCntMc(A, totalCnt_f, ds, &igr_total_cnt);
        cmd = DRV_IOR(DsIrmMiscThrdMc_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), ds);
        GetDsIrmMiscThrdMc(A, c2cThrd_f, ds, &c2c_packet_thrd);
        GetDsIrmMiscThrdMc(A, criticalThrd_f, ds, &critical_packet_thrd);
        GetDsIrmMiscThrdMc(A, totalThrd_f, ds, &igr_total_thrd);
        tbl_cnt_id = DsIrmScCntMc_t;
        field_cnt_id = DsIrmScCntMc_g_0_scCnt_f;
        tbl_thd_id = DsIrmScThrdMc_t;
        field_thd_id = DsIrmScThrdMc_g_0_scThrd_f;
    }

    CTC_DKITS_PRINT_FILE(p_wf, "\n-----------------------------------\n");
    CTC_DKITS_PRINT_FILE(p_wf, "%-14s %-10s %-10s\n", "Type", "Depth", "Thrd");
    CTC_DKITS_PRINT_FILE(p_wf, "-----------------------------------\n");
    CTC_DKITS_PRINT_FILE(p_wf, "%-14s %-10d %-10d\n", "Total", igr_total_cnt, igr_total_thrd);
    CTC_DKITS_PRINT_FILE(p_wf, "%-14s %-10d %-10d\n", "Critical", critical_packet_cnt, critical_packet_thrd);
    CTC_DKITS_PRINT_FILE(p_wf, "%-14s %-10d %-10d\n", "C2C", c2c_packet_cnt, c2c_packet_thrd);

    for (i = 0; i< 4; i++)
    {
        cmd = DRV_IOR(tbl_thd_id, field_thd_id + i);
        DRV_FIELD_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &sc_packet_thrd);
        cmd = DRV_IOR(tbl_cnt_id, field_cnt_id + i);
        DRV_FIELD_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &sc_packet_cnt);
        sal_sprintf(desc, "%s%d", "SC", i);
        CTC_DKITS_PRINT_FILE(p_wf, "%-14s %-10d %-10d\n", desc, sc_packet_cnt, sc_packet_thrd);
    }

    if (is_uc)
    {
        cmd = DRV_IOR(DsIrmHeadroomCnt_t, DsIrmHeadroomCnt_headroomCnt_f);
        DRV_FIELD_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &rt_packet_cnt);
        cmd = DRV_IOR(DsIrmHeadroomThrd_t, DsIrmHeadroomThrd_headroomThrd_f);
        DRV_FIELD_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &rt_packet_thrd);
        CTC_DKITS_PRINT_FILE(p_wf, "%-14s %-10d %-10d\n", "RT", rt_packet_cnt, rt_packet_thrd);
    }

    return CLI_SUCCESS;
}

STATIC int32
_ctc_at_dkit_get_q_depth_igr_detail(uint8 lchip, uint16 gport, sal_file_t p_wf, bool is_uc)
{
    uint32 cmd = 0;
    uint32 channel = 0;
    uint32 depth = 0;
    uint32 local_phy_port = 0;
    uint32 gchip = 0;
    uint32 i = 0;
    uint32 port_thrd = 0;
    bool b_all_zero = TRUE;
    uint8 dp_id = 0;
    uint8 pp_id = 0;
    uint16 sub_chan_id = 0;
    uint32 tbl_cnt_id = 0;
    uint32 field_cnt_id = 0;
    uint32 tbl_thd_id = 0;
    uint32 field_thd_id = 0;
    uint32 pp_dest_port = 0;

    tbl_cnt_id = (is_uc? DsIrmPortCntUc_t: DsIrmPortCntMc_t);
    field_cnt_id = (is_uc? DsIrmPortCntUc_portCnt_f: DsIrmPortCntMc_portCnt_f);
    tbl_thd_id = (is_uc? DsIrmPortLimitedThrdProfileUc_t: DsIrmPortLimitedThrdProfileMc_t);
    field_thd_id = (is_uc? DsIrmPortLimitedThrdProfileUc_g_0_portLimitedThrd_f: DsIrmPortLimitedThrdProfileMc_g_0_portLimitedThrd_f);
    if (0xFFFF == gport)
    {
        CTC_DKITS_PRINT_FILE(p_wf, "\n--------------------------------------\n");
         CTC_DKITS_PRINT_FILE(p_wf, "%-10s%-10s%-10s%-10s%-10s\n", "SrcCore","Port", "Channel", "Depth", "Thrd");
        CTC_DKITS_PRINT_FILE(p_wf, "--------------------------------------\n");
        for (i = 0; i < CTC_DKIT_ONE_SLICE_CHANNEL_NUM; i++)
        {
            _ctc_at_dkit_get_sub_channel_by_channel(lchip, i, &sub_chan_id);
            dp_id = CTC_DKIT_CHAN_TO_DP_ID(sub_chan_id);
            pp_id = CTC_DKIT_CHAN_TO_PP_ID(sub_chan_id);
            sub_chan_id &= CTC_DKIT_SUB_CHAN_MASK;
            lchip = drv_vchip_get_pp_base(lchip) + (pp_id);
            cmd = DRV_IOR(tbl_cnt_id, field_cnt_id);
            DRV_FIELD_IOCTL(lchip, sub_chan_id, DRV_CMD_DP_EN(cmd, dp_id), &depth);
            if (depth)
            {
                cmd = DRV_IOR(IpeHeaderAdjustPhyPortMap_t, IpeHeaderAdjustPhyPortMap_localPhyPort_f);
                DRV_FIELD_IOCTL(lchip, i, DRV_CMD_PP_EN(cmd), &local_phy_port);

                cmd = DRV_IOR(DsIpeFwdDestPortMap_t, DsIpeFwdDestPortMap_ppDestPort_f);
                DRV_FIELD_IOCTL(lchip, local_phy_port, DRV_CMD_PP_EN(cmd), &pp_dest_port);

                if((pp_dest_port != i) || 510 == pp_dest_port)
                {
                    continue;
                }
                CTC_DKIT_GET_GCHIP(lchip, gchip);

                cmd = DRV_IOR(tbl_thd_id, field_thd_id);
                DRV_FIELD_IOCTL(lchip, sub_chan_id, DRV_CMD_DP_EN(cmd, dp_id), &port_thrd);

                CTC_DKITS_PRINT_FILE(p_wf, "%-10d0x%04x    %-10d%-10d%-10d\n",
                                     pp_id/4, CTC_DKIT_DRV_LPORT_TO_CTC_GPORT(gchip, local_phy_port),
                                     i, depth, (port_thrd << 3));
                b_all_zero = FALSE;
            }

        }
        if (b_all_zero)
        {
            CTC_DKITS_PRINT_FILE(p_wf, "All port depth is zero!!!\n");
        }
        CTC_DKITS_PRINT_FILE(p_wf, "--------------------------------------\n");
    }
    else
    {
        channel = _ctc_at_dkit_get_channel_by_gport(lchip, gport, 1);
        if (channel != 0xFFFFFFFF)
        {
            _ctc_at_dkit_get_sub_channel_by_channel(lchip, channel, &sub_chan_id);
            dp_id = CTC_DKIT_CHAN_TO_DP_ID(sub_chan_id);
            pp_id = CTC_DKIT_CHAN_TO_PP_ID(sub_chan_id);
            sub_chan_id &= CTC_DKIT_SUB_CHAN_MASK;
            lchip = drv_vchip_get_pp_base(lchip) + (pp_id);
            cmd = DRV_IOR(tbl_cnt_id, field_cnt_id);
            DRV_FIELD_IOCTL(lchip, sub_chan_id, DRV_CMD_DP_EN(cmd, dp_id), &depth);
            cmd = DRV_IOR(tbl_thd_id, field_thd_id);
            DRV_FIELD_IOCTL(lchip, sub_chan_id, DRV_CMD_DP_EN(cmd, dp_id), &port_thrd);
            lchip = 0;

            CTC_DKITS_PRINT_FILE(p_wf, "\n--------------------------------------\n");
            CTC_DKITS_PRINT_FILE(p_wf, "%-10s%-10s%-10s%-10s%-10s\n", "SrcCore", "Port", "Channel", "Depth", "Thrd");
            CTC_DKITS_PRINT_FILE(p_wf, "--------------------------------------\n");
            CTC_DKITS_PRINT_FILE(p_wf, "%-10d0x%04x    %-10d%-10d%-10d\n", pp_id/4, gport, channel, depth, (port_thrd<<3));
            _ctc_at_dkit_get_q_depth_igr_detail_port_tc(lchip, channel, p_wf, is_uc);
        }
        else
        {
            CTC_DKITS_PRINT_FILE(p_wf, "Invalid Gport:0x%x!!!\n", gport);
        }
    }

    return CLI_SUCCESS;
}

STATIC int32
_ctc_at_dkit_get_q_depth_igr(uint8 lchip, uint16 gport, sal_file_t p_wf, bool is_uc)
{
    uint32 cmd = 0;
    uint32 resrc_mgr_en = 0;
    uint32 tbl_id = 0;
    uint32 field_id = 0;

    tbl_id = (is_uc? IrmMiscCtlUc_t: IrmMiscCtlMc_t);
    field_id = (is_uc? IrmMiscCtlUc_resourceCheckEn_f: IrmMiscCtlMc_resourceCheckEn_f);
    cmd = DRV_IOR(tbl_id, field_id);
    DRV_FIELD_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &resrc_mgr_en);
    if (!resrc_mgr_en)
    {
        CTC_DKITS_PRINT_FILE(p_wf, "Ingress Resouce Mamager is Disable!!!\n");
        return CLI_SUCCESS;
    }
    if (0xFFFF == gport)
    {
        _ctc_at_dkit_get_q_depth_igr_summary(lchip, p_wf, is_uc);
    }
    _ctc_at_dkit_get_q_depth_igr_detail(lchip, gport, p_wf, is_uc);

    return CLI_SUCCESS;
}

int32
ctc_at_dkits_get_q_depth_igr(uint8 lchip, uint16 gport, sal_file_t p_wf)
{
    CTC_DKITS_PRINT_FILE(p_wf, "\n ingress uc resource info \n");
    _ctc_at_dkit_get_q_depth_igr(lchip, gport, p_wf, TRUE);
    CTC_DKITS_PRINT_FILE(p_wf, "\n ingress mc resource info \n");
    _ctc_at_dkit_get_q_depth_igr(lchip, gport, p_wf, FALSE);

    return CLI_SUCCESS;
}

STATIC int32
_ctc_at_dkit_get_q_depth_egr_detail_queue(uint8 lchip, uint16 channel, sal_file_t p_wf, bool is_uc)
{
    uint32 cmd = 0;
    uint32 depth_core0 = 0;
    uint32 depth_core1 = 0;
    uint32 i = 0;
    uint32 q_id = 0;
    uint32 queue_thrd = 0;
    uint16 sub_chan_id = 0;
    uint8 pp_id = 0;
    uint8 dp_id = 0;
    uint8 queue_num = 0;
    uint32 tbl_thd_id =0;
    uint32 field_thd_id = 0;
    uint32 tbl_cnt_id =0;
    uint32 field_cnt_id = 0;

    _ctc_at_dkit_get_sub_channel_by_channel(lchip, channel, &sub_chan_id);
    dp_id = CTC_DKIT_CHAN_TO_DP_ID(sub_chan_id);
    pp_id = CTC_DKIT_CHAN_TO_PP_ID(sub_chan_id);
    sub_chan_id &= CTC_DKIT_SUB_CHAN_MASK;
    lchip = drv_vchip_get_pp_base(lchip) + (pp_id);
    queue_num = (is_uc? 12: 6);
    tbl_thd_id = (is_uc? DsErmQueueThrdProfileUc_t: DsErmQueueLimitedThrdProfileMc_t);
    field_thd_id = (is_uc? DsErmQueueThrdProfileUc_g_0_queueLimitedThrd_f: DsErmQueueLimitedThrdProfileMc_g_0_queueLimitedThrd_f);
    tbl_cnt_id = (is_uc? DsErmQueueCntUc_t: DsErmQueueCntMc_t);
    field_cnt_id = (is_uc? DsErmQueueCntUc_queueCnt_f: DsErmQueueCntMc_g_0_queueCnt_f);
    CTC_DKITS_PRINT_FILE(p_wf, "\n-----------------------------------------------\n");
    CTC_DKITS_PRINT_FILE(p_wf, "%-10s%-10s%-10s%-10s\n", "SrcCore","Q-Id", "Depth", "Queue-Drop-Thrd");
    CTC_DKITS_PRINT_FILE(p_wf, "------------------------------------------------\n");
    for (i = 0; i < queue_num; i++)
    {
        q_id = (is_uc? sub_chan_id * queue_num + i: ((sub_chan_id+(pp_id*2 + (dp_id&0x1)) * 26) * queue_num + i));
        cmd = DRV_IOR(tbl_cnt_id, field_cnt_id);
        DRV_FIELD_IOCTL(lchip, q_id, (is_uc? DRV_CMD_DP_EN(cmd, dp_id): DRV_CMD_PP_EN(cmd)), &depth_core0);
        if (is_uc && (drv_vchip_get_core_num(lchip) > 1))
        {
            uint8 _dual_core_lchip = 0;
            CTC_DKIT_VCHIP_DUAL_CORE_LCHIP_MAP(lchip, _dual_core_lchip);
            cmd = DRV_IOW(tbl_cnt_id, DRV_ENTRY_FLAG);
            DRV_FIELD_IOCTL(_dual_core_lchip, DRV_INS(1, sub_chan_id), DRV_CMD_PP_EN(cmd), &depth_core1);
        }
        cmd = DRV_IOR(tbl_thd_id, field_thd_id);
        DRV_FIELD_IOCTL(lchip, q_id, (is_uc? DRV_CMD_DP_EN(cmd, dp_id): DRV_CMD_PP_EN(cmd)), &queue_thrd);
        CTC_DKITS_PRINT_FILE(p_wf, "%-10d%-10d%-10d%-10d\n", pp_id/4, q_id, depth_core0, (queue_thrd << 3));
        CTC_DKITS_PRINT_FILE(p_wf, "%-10d%-10d%-10d%-10d\n", !(pp_id/4), q_id, depth_core1, (queue_thrd << 3));
    }

    return CLI_SUCCESS;
}


STATIC int32
_ctc_at_dkit_get_q_depth_egr_summary(uint8 lchip, sal_file_t p_wf, bool is_uc)
{
    uint32 cmd = 0;
    uint8 i = 0;
    uint8 step = 0;
    char desc[16] = {0};
    uint32 c2c_packet_cnt = 0;
    uint32 critical_packet_cnt = 0;
    uint32 egr_total_cnt = 0;
    uint32 c2c_packet_thrd = 0;
    uint32 critical_packet_thrd = 0;
    uint32 egr_total_thrd = 0;
    uint32 sc_packet_cnt = 0;
    uint32 sc_packet_thrd = 0;
    uint32 tbl_cnt_id = 0;
    uint32 field_cnt_id = 0;
    uint32 tbl_thd_id = 0;
    uint32 field_thd_id = 0;
    ds_t ds={0};

    if (is_uc)
    {
        cmd = DRV_IOR(DsErmMiscCntUc_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), ds);
        GetDsErmMiscCntUc(A, c2cCnt_f, ds, &c2c_packet_cnt);
        GetDsErmMiscCntUc(A, criticalCnt_f, ds, &critical_packet_cnt);
        GetDsErmMiscCntUc(A, totalCnt_f, ds, &egr_total_cnt);
        cmd = DRV_IOR(DsErmMiscThrdUc_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), ds);
        GetDsErmMiscThrdUc(A, c2cThrd_f, ds, &c2c_packet_thrd);
        GetDsErmMiscThrdUc(A, criticalThrd_f, ds, &critical_packet_thrd);
        GetDsErmMiscThrdUc(A, totalThrd_f, ds, &egr_total_thrd);
        tbl_cnt_id = DsErmScCntUc_t;
        field_cnt_id = DsErmScCntUc_g_0_scCnt_f;
        tbl_thd_id = DsErmScThrdUc_t;
        field_thd_id = DsErmScThrdUc_g_0_scThrd_f;
    }
    else
    {
        cmd = DRV_IOR(DsErmMiscCntMc_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), ds);
        GetDsErmMiscCntMc(A, g_0_c2cCnt_f, ds, &c2c_packet_cnt);
        GetDsErmMiscCntMc(A, g_0_criticalCnt_f, ds, &critical_packet_cnt);
        GetDsErmMiscCntMc(A, g_0_totalCnt_f, ds, &egr_total_cnt);
        cmd = DRV_IOR(DsErmMiscThrdMc_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), ds);
        GetDsErmMiscThrdMc(A, g_0_c2cThrd_f, ds, &c2c_packet_thrd);
        GetDsErmMiscThrdMc(A, g_0_criticalThrd_f, ds, &critical_packet_thrd);
        GetDsErmMiscThrdMc(A, g_0_totalThrd_f, ds, &egr_total_thrd);
        tbl_cnt_id = DsErmScCntMc_t;
        field_cnt_id = DsErmScCntMc_g_0_scCnt_f;
        tbl_thd_id = DsErmScThrdMc_t;
        field_thd_id = DsErmScThrdMc_g_0_scThrd_f;
    }

    CTC_DKITS_PRINT_FILE(p_wf, "\n-----------------------------------\n");
    CTC_DKITS_PRINT_FILE(p_wf, "%-14s %-10s %-10s\n", "Type", "Depth", "Thrd");
    CTC_DKITS_PRINT_FILE(p_wf, "-----------------------------------\n");
    CTC_DKITS_PRINT_FILE(p_wf, "%-14s %-10d %-10d\n", "Total", egr_total_cnt, egr_total_thrd);
    CTC_DKITS_PRINT_FILE(p_wf, "%-14s %-10d %-10d\n", "Critical", critical_packet_cnt, critical_packet_thrd);
    CTC_DKITS_PRINT_FILE(p_wf, "%-14s %-10d %-10d\n", "C2C", c2c_packet_cnt, c2c_packet_thrd);
    step = DsErmScThrdUc_g_1_scThrd_f - DsErmScThrdUc_g_0_scThrd_f;
    for (i = 0; i< 4; i++)
    {
        cmd = DRV_IOR(tbl_thd_id, field_thd_id + (step*i));
        DRV_FIELD_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &sc_packet_thrd);
        cmd = DRV_IOR(tbl_cnt_id, field_cnt_id + i);
        DRV_FIELD_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &sc_packet_cnt);
        sal_sprintf(desc, "%s%d", "SC", i);
        CTC_DKITS_PRINT_FILE(p_wf, "%-14s %-10d %-10d\n", desc, sc_packet_cnt, sc_packet_thrd);
    }

    return CLI_SUCCESS;
}

STATIC int32
_ctc_at_dkit_get_q_depth_egr_detail(uint8 lchip, uint16 gport, sal_file_t p_wf, bool is_uc)
{
    uint32 entry_num = 0;
    uint32 cmd = 0;
    uint32 channel = 0;
    uint32 depth_core0 = 0;
    uint32 depth_core1 = 0;
    uint32 local_phy_port = 0;
    uint32 gchip = 0;
    uint32 i = 0;
    uint32 port_thrd = 0;
    bool b_all_zero = TRUE;
    uint8 dp_id = 0;
    uint8 pp_id = 0;
    uint16 sub_chan_id = 0;
    uint16 core_chan = 0;
    uint32 tbl_cnt_id = 0;
    uint32 field_cnt_id = 0;
    uint32 tbl_thd_id = 0;
    uint32 field_thd_id = 0;
    uint32 pp_dest_port = 0;

    tbl_cnt_id = (is_uc? DsErmPortCntUc_t: DsErmPortCntMc_t);
    field_cnt_id = (is_uc? DsErmPortCntUc_portCnt_f: DsErmPortCntMc_g_0_portCnt_f);
    tbl_thd_id = (is_uc? DsErmPortThrdProfileUc_t: DsErmPortLimitedThrdProfileMc_t);
    field_thd_id = (is_uc? DsErmPortThrdProfileUc_g_0_portLimitedThrd_f: DsErmPortLimitedThrdProfileMc_g_0_portLimitedThrd_f);
    entry_num = DRV_TABLE_MAX_INDEX(lchip, tbl_cnt_id) / 2;
    if (0xFFFF == gport)
    {
        CTC_DKITS_PRINT_FILE(p_wf, "\n--------------------------------------\n");
        CTC_DKITS_PRINT_FILE(p_wf, "%-10s%-10s%-10s%-10s%-10s\n", "SrcCore", "Port", "Channel", "Depth", "Thrd");
        CTC_DKITS_PRINT_FILE(p_wf, "--------------------------------------\n");
        for (i = 0; i < CTC_DKIT_ONE_SLICE_CHANNEL_NUM; i++)
        {
            _ctc_at_dkit_get_sub_channel_by_channel(lchip, i, &sub_chan_id);
            dp_id = CTC_DKIT_CHAN_TO_DP_ID(sub_chan_id);
            pp_id = CTC_DKIT_CHAN_TO_PP_ID(sub_chan_id);
            sub_chan_id &= CTC_DKIT_SUB_CHAN_MASK;
            core_chan = sub_chan_id + (pp_id * 2 + (dp_id & 0x1)) * 26;
            lchip = drv_vchip_get_pp_base(lchip) + (pp_id);
            cmd = DRV_IOR(tbl_cnt_id, field_cnt_id);
            DRV_FIELD_IOCTL(lchip, (is_uc? sub_chan_id: core_chan), (is_uc? DRV_CMD_DP_EN(cmd, dp_id): DRV_CMD_PP_EN(cmd)), &depth_core0);
            if (drv_vchip_get_core_num(lchip) > 1)
            {
                uint8 _dual_core_lchip = 0;
                CTC_DKIT_VCHIP_DUAL_CORE_LCHIP_MAP(lchip, _dual_core_lchip);
                cmd = DRV_IOR(tbl_cnt_id, field_cnt_id);
                DRV_FIELD_IOCTL(_dual_core_lchip, is_uc ? (entry_num +  sub_chan_id): (entry_num + core_chan), (is_uc? DRV_CMD_DP_EN(cmd, dp_id): DRV_CMD_PP_EN(cmd)), &depth_core1);
            }
            if (depth_core0 || depth_core1)
            {
                cmd = DRV_IOR(EpeHeaderAdjustPhyPortMap_t, EpeHeaderAdjustPhyPortMap_localPhyPort_f);
                DRV_FIELD_IOCTL(lchip, i, DRV_CMD_PP_EN(cmd), &local_phy_port);

                cmd = DRV_IOR(DsIpeFwdDestPortMap_t, DsIpeFwdDestPortMap_ppDestPort_f);
                DRV_FIELD_IOCTL(lchip, local_phy_port, DRV_CMD_PP_EN(cmd), &pp_dest_port);

                if((pp_dest_port != i) || 510 == pp_dest_port)
                {
                    continue;
                }
                CTC_DKIT_GET_GCHIP(lchip, gchip);

                cmd = DRV_IOR(tbl_thd_id, field_thd_id);
                DRV_FIELD_IOCTL(lchip, (is_uc? sub_chan_id: core_chan), (is_uc? DRV_CMD_DP_EN(cmd, dp_id): DRV_CMD_PP_EN(cmd)), &port_thrd);
            }
            if (depth_core0)
            {
                CTC_DKITS_PRINT_FILE(p_wf, "%-10d0x%04x    %-10d%-10d%-10d\n",
                                     pp_id/4, CTC_DKIT_DRV_LPORT_TO_CTC_GPORT(gchip, local_phy_port),
                                     i, depth_core0, (port_thrd << 3));
                b_all_zero = FALSE;
            }
            if (depth_core1)
            {
                CTC_DKITS_PRINT_FILE(p_wf, "%-10d0x%04x    %-10d%-10d%-10d\n",
                                     !(pp_id/4), CTC_DKIT_DRV_LPORT_TO_CTC_GPORT(gchip, local_phy_port),
                                     i, depth_core1, (port_thrd << 3));
                b_all_zero = FALSE;
            }
        }
        if (b_all_zero)
        {
            CTC_DKITS_PRINT_FILE(p_wf, "All port depth is zero!!!\n");
        }
        CTC_DKITS_PRINT_FILE(p_wf, "--------------------------------------\n");
    }
    else
    {
        channel = _ctc_at_dkit_get_channel_by_gport(lchip, gport, 0);
        if (channel != 0xFFFFFFFF)
        {
            _ctc_at_dkit_get_sub_channel_by_channel(lchip, channel, &sub_chan_id);
            dp_id = CTC_DKIT_CHAN_TO_DP_ID(sub_chan_id);
            pp_id = CTC_DKIT_CHAN_TO_PP_ID(sub_chan_id);
            sub_chan_id &= CTC_DKIT_SUB_CHAN_MASK;
            core_chan = sub_chan_id + (pp_id * 2 + (dp_id & 0x1)) * 26;
            cmd = DRV_IOR(tbl_cnt_id, field_cnt_id);
            DRV_FIELD_IOCTL(drv_vchip_get_pp_base(lchip) + (pp_id), (is_uc? sub_chan_id: core_chan), 
                           (is_uc? DRV_CMD_DP_EN(cmd, dp_id): DRV_CMD_PP_EN(cmd)), &depth_core0);
            if ((drv_vchip_get_core_num(drv_vchip_get_pp_base(lchip) + (pp_id)) > 1))
            {
                uint8 _dual_core_lchip = 0;
                CTC_DKIT_VCHIP_DUAL_CORE_LCHIP_MAP((drv_vchip_get_pp_base(lchip) + (pp_id)), _dual_core_lchip);
                cmd = DRV_IOR(tbl_cnt_id, field_cnt_id);
                DRV_FIELD_IOCTL(_dual_core_lchip, is_uc ? (entry_num +  sub_chan_id): (entry_num + core_chan), (is_uc? DRV_CMD_DP_EN(cmd, dp_id): DRV_CMD_PP_EN(cmd)), &depth_core1);
            }
            cmd = DRV_IOR(tbl_thd_id, field_thd_id);
            DRV_FIELD_IOCTL(drv_vchip_get_pp_base(lchip) + (pp_id), (is_uc? sub_chan_id: core_chan), 
                           (is_uc? DRV_CMD_DP_EN(cmd, dp_id): DRV_CMD_PP_EN(cmd)), &port_thrd);
            CTC_DKITS_PRINT_FILE(p_wf, "\n--------------------------------------\n");
            CTC_DKITS_PRINT_FILE(p_wf, "%-10s%-10s%-10s%-10s%-10s\n", "SrcCore", "Port", "Channel", "Depth", "Thrd");
            CTC_DKITS_PRINT_FILE(p_wf, "--------------------------------------\n");
            CTC_DKITS_PRINT_FILE(p_wf, "%-10d0x%04x    %-10d%-10d%-10d\n", pp_id/4, gport, channel, depth_core0, (port_thrd<<3));
            CTC_DKITS_PRINT_FILE(p_wf, "%-10d0x%04x    %-10d%-10d%-10d\n", !(pp_id/4), gport, channel, depth_core1, (port_thrd<<3));
            _ctc_at_dkit_get_q_depth_egr_detail_queue(lchip, channel, p_wf, is_uc);
        }
        else
        {
            CTC_DKITS_PRINT_FILE(p_wf, "Invalid Gport:0x%x!!!\n", gport);
        }
    }

    return CLI_SUCCESS;
}

STATIC int32
_ctc_at_dkit_get_q_depth_egr(uint8 lchip, uint16 gport, sal_file_t p_wf, bool is_uc)
{
    uint32 cmd = 0;
    uint32 resrc_mgr_en = 0;
    uint32 tbl_id = 0;
    uint32 field_id = 0;

    tbl_id = (is_uc? ErmMiscCtlUc_t: ErmMiscCtlMc_t);
    field_id = (is_uc? ErmMiscCtlUc_resourceCheckEn_f: ErmMiscCtlMc_resourceCheckEn_f);
    cmd = DRV_IOR(tbl_id, field_id);
    DRV_FIELD_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &resrc_mgr_en);
    if (!resrc_mgr_en)
    {
        CTC_DKITS_PRINT_FILE(p_wf, "Egress Resouce Mamager is Disable!!!\n");
        return CLI_SUCCESS;
    }
    if (0xFFFF == gport)
    {
        _ctc_at_dkit_get_q_depth_egr_summary(lchip, p_wf, is_uc);
    }
    _ctc_at_dkit_get_q_depth_egr_detail(lchip, gport, p_wf, is_uc);

    return CLI_SUCCESS;
}

int32
ctc_at_dkits_get_q_depth_egr(uint8 lchip, uint16 gport, sal_file_t p_wf)
{
    CTC_DKITS_PRINT_FILE(p_wf, "\n egress uc resource info \n");
    _ctc_at_dkit_get_q_depth_egr(lchip, gport, p_wf, TRUE);
    CTC_DKITS_PRINT_FILE(p_wf, "\n egress mc resource info \n");
    _ctc_at_dkit_get_q_depth_egr(lchip, gport, p_wf, FALSE);

    return CLI_SUCCESS;
}

int32
ctc_at_dkit_show_queue_depth(uint8 lchip, sal_file_t p_wf)
{
    uint32 local_phy_port = 0;
    uint32 gport = 0;
    uint32 entry_num = 0;
    uint32 idx = 0;
    uint32 cmd = 0;
    bool b_all_zero = TRUE;
    uint32 value = 0;
    uint32 value1 = 0;
    uint8 dp_id = 0;
    uint8 core_id = 0;
    uint16 pp_chan = 0;
    uint8 dp_chan = 0;
    uint8 pp_id   = 0;
    uint8 ucqfst  = 0;
    uint8 mcqfst  = 0;
    uint8 pp_num = drv_vchip_get_pp_num(lchip);
    uint8 core_num = drv_vchip_get_core_num(lchip);
    uint8 lchip_tmp = 0;
    uint8 gchip = 0;
    uint16 chan_id = 0;
    DsQMgrQueIdMap_m qid_map;
    DsQMgrQueSchMap_m sch_map;
    uint32 schoffset = 0;
    uint32 queue_id = 0;
    uint32 cos_sel = 0;
    uint32 nor_que_num = CTC_DKIT_PER_DP_CHANNEL_NUM * CTC_DKIT_DP_MAX_NUM * pp_num * CTC_DKIT_QOS_QUEUE_NUM_PER_CHAN;

    CTC_DKIT_GET_GCHIP(lchip, gchip);
    CTC_DKITS_PRINT_FILE(p_wf, "%-7s %-8s %-9s %-9s %-11s %-8s %-6s %-6s %-6s %-11s %-8s %-7s\n", "Port", "ChanId", "QueueID", "QOffset", "ClassPrio", "Type", "Core", "PpId", "DpId", "SubChanId", "InstId", "Depth");
    CTC_DKITS_PRINT_FILE(p_wf, "---------------------------------------------------------------------------------------------------------\n");

    /* NORMAL UC */
    entry_num = DRV_TABLE_MAX_INDEX(lchip, DsErmQueueCntUc_t) / 2;
    for (dp_id = 0; dp_id < pp_num * CTC_DKIT_DP_MAX_NUM; dp_id++)
    {
        pp_id = dp_id / CTC_DKIT_DP_MAX_NUM;
        core_id = pp_id / (pp_num / core_num);
        lchip_tmp = drv_vchip_get_pp_base(lchip) + pp_id;
        for (idx = 0; idx < entry_num; idx++)
        {
            cmd = DRV_IOR(DsErmQueueCntUc_t, DsErmQueueCntUc_queueCnt_f);
            DRV_FIELD_IOCTL(lchip_tmp, idx, DRV_CMD_DP_EN(cmd, dp_id%CTC_DKIT_DP_MAX_NUM), &value);

            if (core_num > 1)
            {
                uint8 _dual_core_lchip = 0;
                CTC_DKIT_VCHIP_DUAL_CORE_LCHIP_MAP(lchip_tmp, _dual_core_lchip);
                DRV_FIELD_IOCTL(_dual_core_lchip, idx + entry_num, DRV_CMD_DP_EN(cmd, dp_id%CTC_DKIT_DP_MAX_NUM), &value1);
            }

            if (0 == (value | value1))
            {
                continue;
            }
            b_all_zero = FALSE;

            ucqfst  = idx % CTC_DKIT_PER_CHAN_UC_QUEUE_NUM;
            dp_chan = idx / CTC_DKIT_PER_CHAN_UC_QUEUE_NUM;
            pp_chan = (dp_id % CTC_DKIT_DP_MAX_NUM) * CTC_DKIT_PER_DP_CHANNEL_NUM + dp_chan;
            _ctc_at_get_channel_by_sub_channel(lchip_tmp, dp_chan, dp_id, &chan_id);

            cmd = DRV_IOR(DsQMgrQueIdMap_t, DRV_ENTRY_FLAG);
            DRV_IOCTL(lchip_tmp, pp_chan * CTC_DKIT_ENQ_MODEL_QUEUE_NUM + ucqfst, DRV_CMD_PP_EN(cmd), &qid_map);
            schoffset = GetDsQMgrQueIdMap(V, schOffset_f, &qid_map);
            cmd = DRV_IOR(DsQMgrQueSchMap_t, DRV_ENTRY_FLAG);
            DRV_IOCTL(lchip_tmp, pp_chan, DRV_CMD_PP_EN(cmd), &sch_map);
            cos_sel = (GetDsQMgrQueSchMap(V, cosSel_f, &sch_map) & (1 << schoffset)) ? 1 : 0;

            queue_id = (dp_id * CTC_DKIT_PER_DP_CHANNEL_NUM + dp_chan) * CTC_DKIT_QOS_QUEUE_NUM_PER_CHAN + schoffset + cos_sel;

            cmd = DRV_IOR(EpeHeaderAdjustPhyPortMap_t, EpeHeaderAdjustPhyPortMap_localPhyPort_f);
            DRV_FIELD_IOCTL(lchip, chan_id, DRV_CMD_PP_EN(cmd), &local_phy_port);
            gport = CTC_DKIT_DRV_LPORT_TO_CTC_GPORT(gchip, local_phy_port);

            if (0 != value)
            {
                CTC_DKITS_PRINT_FILE(p_wf, "0x%04x  %-8d %-9d %-9d %-11d %-8s %-6d %-6d %-6d %-11d %-8d %-7d\n", 
                                     gport, chan_id, queue_id, ucqfst, !cos_sel, "UC", core_id, pp_id % (pp_num / core_num), dp_id % CTC_DKIT_DP_MAX_NUM, dp_chan, 0, value);
            }
            if (0 != value1)
            {
                CTC_DKITS_PRINT_FILE(p_wf, "0x%04x  %-8d %-9d %-9d %-11d %-8s %-6d %-6d %-6d %-11d %-8d %-7d\n", 
                                     gport, chan_id, queue_id, ucqfst, !cos_sel, "UC", core_id, pp_id % (pp_num / core_num), dp_id % CTC_DKIT_DP_MAX_NUM, dp_chan, 1, value1);
            }
        }
    }

    /* NORMAL MC */
    entry_num = DRV_TABLE_MAX_INDEX(lchip, DsErmQueueCntMc_t) / 2;
    for (core_id = 0; core_id < core_num; core_id++)
    {
        lchip_tmp = drv_vchip_get_pp_base(lchip) + (pp_num / core_num) * core_id;
        for (idx = 0; idx < entry_num; idx++)
        {
            cmd = DRV_IOR(DsErmQueueCntMc_t, DsErmQueueCntMc_g_0_queueCnt_f);
            DRV_FIELD_IOCTL(lchip_tmp, idx, DRV_CMD_PP_EN(cmd), &value);

            if (core_num > 1)
            {
                uint8 _dual_core_lchip = 0;
                CTC_DKIT_VCHIP_DUAL_CORE_LCHIP_MAP(lchip_tmp, _dual_core_lchip);
                DRV_FIELD_IOCTL(_dual_core_lchip, idx + entry_num, DRV_CMD_PP_EN(cmd), &value1);
            }

            if (0 == (value | value1))
            {
                continue;
            }
            b_all_zero = FALSE;

            mcqfst  = idx % CTC_DKIT_PER_CHAN_MC_QUEUE_NUM;
            dp_id = idx / (CTC_DKIT_PER_CHAN_MC_QUEUE_NUM * CTC_DKIT_PER_DP_CHANNEL_NUM)
                  + core_id * (pp_num / core_num * CTC_DKIT_DP_MAX_NUM);
            pp_id = dp_id / CTC_DKIT_DP_MAX_NUM;
            dp_chan = idx / CTC_DKIT_PER_CHAN_MC_QUEUE_NUM % CTC_DKIT_PER_DP_CHANNEL_NUM;
            pp_chan = (dp_id % CTC_DKIT_DP_MAX_NUM) * CTC_DKIT_PER_DP_CHANNEL_NUM + dp_chan;

            lchip_tmp = drv_vchip_get_pp_base(lchip) + pp_id;
            _ctc_at_get_channel_by_sub_channel(lchip_tmp, dp_chan, dp_id, &chan_id);
            
            cmd = DRV_IOR(DsQMgrQueIdMap_t, DRV_ENTRY_FLAG);
            DRV_IOCTL(lchip_tmp, pp_chan * CTC_DKIT_ENQ_MODEL_QUEUE_NUM + mcqfst + CTC_DKIT_PER_CHAN_UC_QUEUE_NUM, DRV_CMD_PP_EN(cmd), &qid_map);
            schoffset = GetDsQMgrQueIdMap(V, schOffset_f, &qid_map);
            cmd = DRV_IOR(DsQMgrQueSchMap_t, DRV_ENTRY_FLAG);
            DRV_IOCTL(lchip_tmp, pp_chan, DRV_CMD_PP_EN(cmd), &sch_map);
            cos_sel = GetDsQMgrQueSchMap(V, cosSel_f, &sch_map);

            queue_id = (dp_id * CTC_DKIT_PER_DP_CHANNEL_NUM + dp_chan) * CTC_DKIT_QOS_QUEUE_NUM_PER_CHAN + schoffset + ((cos_sel & (1 << schoffset)) ? 1 : 0);

            cmd = DRV_IOR(EpeHeaderAdjustPhyPortMap_t, EpeHeaderAdjustPhyPortMap_localPhyPort_f);
            DRV_FIELD_IOCTL(lchip, chan_id, DRV_CMD_PP_EN(cmd), &local_phy_port);
            gport = CTC_DKIT_DRV_LPORT_TO_CTC_GPORT(gchip, local_phy_port);

            if (0 != value)
            {
                CTC_DKITS_PRINT_FILE(p_wf, "0x%04x  %-8d %-9d %-9d %-11d %-8s %-6d %-6d %-6d %-11d %-8d %-7d\n", 
                                     gport, chan_id, queue_id, mcqfst, !cos_sel, "MC", core_id, pp_id % (pp_num / core_num), dp_id % CTC_DKIT_DP_MAX_NUM, dp_chan, 0, value);
            }
            if (0 != value1)
            {
                CTC_DKITS_PRINT_FILE(p_wf, "0x%04x  %-8d %-9d %-9d %-11d %-8s %-6d %-6d %-6d %-11d %-8d %-7d\n", 
                                     gport, chan_id, queue_id, mcqfst, !cos_sel, "MC", core_id, pp_id % (pp_num / core_num), dp_id % CTC_DKIT_DP_MAX_NUM, dp_chan, 1, value1);
            }
        }
    }

    /* DMA UC */
    entry_num = DRV_TABLE_MAX_INDEX(lchip, DsErmDmaCntUc_t) / 2;
    cmd = DRV_IOR(DsErmDmaCntUc_t, DsErmDmaCntUc_queueCnt_f);
    for (dp_id = 0; dp_id < pp_num * CTC_DKIT_DP_MAX_NUM; dp_id++)
    {
        pp_id = dp_id / CTC_DKIT_DP_MAX_NUM;
        core_id = pp_id / (pp_num / core_num);
        lchip_tmp = drv_vchip_get_pp_base(lchip) + pp_id;
        for (idx = 0; idx < entry_num; idx++)
        {
            DRV_FIELD_IOCTL(lchip_tmp, idx, DRV_CMD_DP_EN(cmd, dp_id%CTC_DKIT_DP_MAX_NUM), &value);

            if (core_num > 1)
            {
                uint8 _dual_core_lchip = 0;
                CTC_DKIT_VCHIP_DUAL_CORE_LCHIP_MAP(lchip_tmp, _dual_core_lchip);
                DRV_FIELD_IOCTL(_dual_core_lchip, idx + entry_num, DRV_CMD_DP_EN(cmd, dp_id%CTC_DKIT_DP_MAX_NUM), &value1);
            }

            queue_id = idx + CTC_DKIT_REASON_TOTAL_QUEUE_NUM + nor_que_num;
            if (0 != value)
            {
                CTC_DKITS_PRINT_FILE(p_wf, "-     %-8d %-9d %-9d %-11d %-8s %-6d %-6d %-6d %-11d %-8d %-7d\n",
                                      CTC_DKIT_CHANID_DMA_RX0, queue_id, idx, 0, "DMA-UC", core_id, pp_id % (pp_num / core_num), dp_id % CTC_DKIT_DP_MAX_NUM, 24, 0, value);
                b_all_zero = FALSE;
            }
            if (0 != value1)
            {
                CTC_DKITS_PRINT_FILE(p_wf, "-     %-8d %-9d %-9d %-11d %-8s %-6d %-6d %-6d %-11d %-8d %-7d\n",
                                     CTC_DKIT_CHANID_DMA_RX0, queue_id, idx, 0, "DMA-UC", core_id, pp_id % (pp_num / core_num), dp_id % CTC_DKIT_DP_MAX_NUM, 24, 1, value1);
                b_all_zero = FALSE;
            }
        }
    }

    /* DMA MC*/
    entry_num = DRV_TABLE_MAX_INDEX(lchip, DsErmDmaCntMc_t);
    cmd = DRV_IOR(DsErmDmaCntMc_t, DsErmDmaCntMc_g_0_queueCnt_f);
    for (core_id = 0; core_id < core_num; core_id++)
    {
        lchip_tmp = drv_vchip_get_pp_base(lchip) + (pp_num / core_num) * core_id;
        for (idx = 0; idx < entry_num; idx++)
        {
            DRV_FIELD_IOCTL(lchip_tmp, idx, DRV_CMD_PP_EN(cmd), &value);
            if (0 != value)
            {
                queue_id = idx + nor_que_num;
                CTC_DKITS_PRINT_FILE(p_wf, "-     %-8d %-9d %-9d %-11d %-8s %-6d %-6d %-6d %-11d %-8d %-7d\n",
                                     CTC_DKIT_CHANID_DMA_RX0, queue_id, idx, 0, "DMA-MC", core_id, 0, 0, 24, 0, value);
                b_all_zero = FALSE;
            }
        }
    }
    if (b_all_zero)
    {
        CTC_DKITS_PRINT_FILE(p_wf, "All Queue depth is zero!!!\n");
    }
    CTC_DKITS_PRINT_FILE(p_wf, "---------------------------------------------------------------------------------------------------------\n");
    return CLI_SUCCESS;
}

STATIC int32
_ctc_at_dkit_get_chanel_by_queue(uint8 lchip, uint16 qofst, uint8 is_uc, uint8 is_net, uint8 index)
{
    DsQMgrQueIdMap_m qid_map;
    DsQMgrQueSchMap_m sch_map;
    uint16 chanid = 0;
    uint16 pp_chan = 0;
    uint16 que_map_idx = 0;
    uint8 sub_chan_id = 0;
    uint32 schoffset = 0;
    uint32 queue_id = 0;
    uint32 cos_sel = 0;
    uint32 cmd = 0;
    uint32 local_phy_port = 0;
    uint32 gport = 0;
    uint8 ucqfst  = 0;
    uint8 mcqfst  = 0;
    uint8 gchip = 0;
    uint8 dp_id = 0;
    uint8 pp_id = 0;
    uint8 dest_dp_id = 0;

    CTC_DKIT_GET_GCHIP(lchip, gchip);
    if (is_net)
    {
        if (is_uc)
        {
            ucqfst = qofst % 12;
            /* uc bits 0-8 queue index, bit 9-12 destDpId bit 13 1 dma, 0 net */
            sub_chan_id = (qofst & 0x1FF)/ 12;
            sub_chan_id &= CTC_DKIT_SUB_CHAN_MASK;
            dest_dp_id = ((qofst>>9)&0x7) + (((qofst) >> 12) & 0x1)*2*(drv_vchip_get_pp_num(lchip)/drv_vchip_get_core_num(lchip));
            dp_id = dest_dp_id % 2;
            pp_id = dest_dp_id / 2;

            que_map_idx = pp_chan * CTC_DKIT_ENQ_MODEL_QUEUE_NUM + ucqfst;
        }
        else
        {
            mcqfst = qofst % 6;
            pp_chan = qofst / 6;
            pp_id =pp_chan / 52;
            dp_id = (pp_chan % 52) / 36;
            sub_chan_id = (pp_chan % 52) % 36;

            que_map_idx = pp_chan * CTC_DKIT_ENQ_MODEL_QUEUE_NUM + CTC_DKIT_PER_CHAN_UC_QUEUE_NUM + mcqfst;
        }
        lchip = drv_vchip_get_pp_base(lchip) + (pp_id);
        _ctc_at_get_channel_by_sub_channel(lchip, sub_chan_id, dp_id, &chanid);

        cmd = DRV_IOR(DsQMgrQueIdMap_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, que_map_idx, DRV_CMD_PP_EN(cmd), &qid_map);
        schoffset = GetDsQMgrQueIdMap(V, schOffset_f, &qid_map);
        cmd = DRV_IOR(DsQMgrQueSchMap_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, pp_chan, DRV_CMD_PP_EN(cmd), &sch_map);
        cos_sel = (GetDsQMgrQueSchMap(V, cosSel_f, &sch_map) & (1 << schoffset)) ? 1 : 0;
        queue_id = (dp_id * CTC_DKIT_PER_DP_CHANNEL_NUM + sub_chan_id) * CTC_DKIT_QOS_QUEUE_NUM_PER_CHAN + schoffset + cos_sel;

        cmd = DRV_IOR(EpeHeaderAdjustPhyPortMap_t, EpeHeaderAdjustPhyPortMap_localPhyPort_f);
        DRV_FIELD_IOCTL(lchip, chanid, DRV_CMD_PP_EN(cmd), &local_phy_port);
        gport = CTC_DKIT_DRV_LPORT_TO_CTC_GPORT(gchip, local_phy_port);
        CTC_DKIT_PRINT("%-6d %-6d %-6d %-11d %-7d %-11d %-10d 0x%04x\n", pp_id/4, pp_id, dp_id, sub_chan_id, queue_id, is_uc ? ucqfst : mcqfst, chanid, gport);
    }
    else
    {
        if (is_uc)
        {
            dest_dp_id = (qofst>>9)&0xF;
            qofst = qofst & 0x1FF;
            dp_id = dest_dp_id % 2;
            pp_id = dest_dp_id / 2;
        }
        else
        {
            qofst = qofst - 2496;
            pp_id = 0;
            dp_id = 0;
        }
        CTC_DKIT_PRINT("%-6d %-6d %-6d %-11d %-7d %-11d %-10d %-6s\n", pp_id/4, pp_id, dp_id, 24, qofst, qofst, 486, "-");
    }

    return CLI_SUCCESS;
}

int32
ctc_at_dkit_show_queue_id(uint8 lchip)
{
    uint32 cmd = 0;
    uint32 qid = 0;
    uint8 i = 0;
    uint8 pp_id = 0;
    uint8 dp_id = 0;
    uint8 is_net_queue = 0;

    /* uc bits 0-8 queue index, bit 9-12 destDpId bit 13 1 dma, 0 net */
    CTC_DKIT_PRINT("\n uc queue id info \n");
    CTC_DKIT_PRINT("%-6s %-6s %-6s %-6s %-6s %-11s %-7s %-11s %-10s %-16s\n", "SrcPp", "SrcDp", "Core", "PpId", "DpId", "SubChanID", "QueID", "QueOffset", "ChanId", "Port");
    CTC_DKIT_PRINT("------------------------------------------------------------------------------------\n");
    for (dp_id = 0; dp_id < drv_vchip_get_pp_num(lchip) * 2; dp_id++)
    {
        for (i = 0; i < 5; i++)
        {
            cmd = DRV_IOR(BufStoreQueueIdMon_t, BufStoreQueueIdMon_g_0_queueIdMon_f + i);
            DRV_FIELD_IOCTL(drv_vchip_get_pp_base(lchip) + (dp_id/2), 0, DRV_CMD_DP_EN(cmd, dp_id%2), &qid);
            is_net_queue = (((qid>>13)&0x1)? 0: 1);
            CTC_DKIT_PRINT("%-6d %-6d ", dp_id/2, dp_id%2);
            _ctc_at_dkit_get_chanel_by_queue(lchip, qid, TRUE, is_net_queue, i);
        }
    }
    /* mc qid < 2496 norma queue 2496 - 2624 dma queue*/
    CTC_DKIT_PRINT("\n mc queue id info \n");
    CTC_DKIT_PRINT("%-6s %-6s %-6s %-6s %-6s %-11s %-7s %-11s %-10s %-16s\n", "SrcPp", "SrcDp", "Core", "PpId", "DpId", "SubChanID", "QueID", "QueOffset", "ChanId", "Port");
    CTC_DKIT_PRINT("------------------------------------------------------------------------------------\n");
    for (pp_id = 0; pp_id < drv_vchip_get_pp_num(lchip); pp_id++)
    {
        for (i = 0; i < 5; i++)
        {
            cmd = DRV_IOR(QMgrQWriteDebugInfo_t, QMgrQWriteDebugInfo_queueIdMon0_f + i);
            DRV_FIELD_IOCTL(drv_vchip_get_pp_base(lchip) + (pp_id), 0, DRV_CMD_PP_EN(cmd), &qid);
            is_net_queue = (qid < 2496? 1: 0);
            CTC_DKIT_PRINT("%-6d %-6s ", pp_id, "-");
            _ctc_at_dkit_get_chanel_by_queue(lchip, qid, FALSE, is_net_queue, i);
        }
    }

    return CLI_SUCCESS;
}

#define ___GET_SENSOR__
#define CTC_DKIT_SENSOR_MAP_LCHIP(lchip, sensor_id) \
    do{\
        (lchip) = drv_vchip_get_pp_base(lchip) + (((sensor_id) >= 6) ? (drv_vchip_get_pp_num(lchip) / 2) : 0);\
    }while(0);

#define CTC_DKIT_SENSOR_VAL_TO_INT32(val) (((val)&0x80000000)? (0 - (int32)((val)&0x7fffffff)):(int32)((val)&0x7fffffff))

struct ctc_dkit_sensor_s
{
    uint8  type;                                   
    uint8  count;
    uint32 value[12];
};
typedef struct ctc_dkit_sensor_s ctc_dkit_sensor_t;

STATIC int32
_sys_at_dkit_get_sensor_tbl_id(uint8 lchip, uint8 sensor_id, uint32* cfg_tbl_id, uint32* data_tbl_id, uint32* width_cfg_tbl_id, uint32* tbl_idx)
{
    if(5 == sensor_id || 11 == sensor_id)
    {
        *cfg_tbl_id = TvsenCfgTop_t;
        *data_tbl_id = TvsenDataRdyTop_t;
        *width_cfg_tbl_id = TvsenStartPulseWidthCfgTop_t;
        *tbl_idx = 0;
    }
    else
    {
        *cfg_tbl_id = TvsenCfg_t;
        *data_tbl_id = TvsenDataRdy_t;
        *width_cfg_tbl_id = TvsenStartPulseWidthCfg_t;
        *tbl_idx = (sensor_id >= 6)?(sensor_id - 6):(sensor_id - 0);
    }

    return CLI_SUCCESS;
}

STATIC int32
_sys_at_dkit_sensor_result_proc(uint8 lchip, uint32* measure_result, uint8 type)
{
    int32 raw_data = 0;
    int32 real_data = 0;

    /* measure_result is a 12-bit signed integer, bit11 is sign bit */
    if ((*measure_result) & 0x800)
    {
        raw_data = 4096 - *measure_result;
    }
    else
    {
        raw_data = (*measure_result) & 0xfff;
    }

    if(CTC_DKIT_MONITOR_SENSOR_TEMP == type)
    {
        if ((*measure_result) & 0x800)
        {
            real_data = (1180000 - raw_data * 950)/10000;
            *measure_result = real_data < 0 ? ((0 - real_data) | (1 << 31)) : (uint32)real_data;
        }
        else
        {
            *measure_result = (1180000 + raw_data * 950)/10000;
        }
    }
    else
    {
        if ((*measure_result) & 0x800)
        {
            *measure_result = (raw_data * (5868)/10000);
        }
        else
        {
            real_data = -(raw_data * (5868)/10000);
            *measure_result = real_data < 0 ? ((0 - real_data) | (1 << 31)) : (uint32)real_data;
        }
    }

    return CLI_SUCCESS;
}

int32
sys_at_dkit_get_chip_sensor(uint8 lchip, void* sensor)
{
    ctc_dkit_sensor_t* p_sensor = (ctc_dkit_sensor_t*)sensor;
    uint32 cmd = 0;
    uint32 cfg_tbl_id, data_tbl_id, width_cfg_tbl_id, tbl_idx;
    uint32 timeout = 0;
    uint32 measure_result = 0;
    uint8 data_rdy = 0;
    uint8 sensor_id = 0;
    uint8 sensor_cnt = 0;
    uint8 i =0;
    TvsenCfg_m senCfg;
    TvsenDataRdy_m senData;
    TvsenStartPulseWidthCfg_m widthCfg;
    uint8 sensor_num;

    /* 12 sensor for dul-core, 6 sensors for single core */
    sensor_num = (drv_get_chip_sub_type(lchip) >= DRV_CHIP_SUB_TYPE_3) ? 12 : 6;
    for (sensor_id = 0; sensor_id < sensor_num; sensor_id++)
    {
        _sys_at_dkit_get_sensor_tbl_id(lchip, sensor_id, &cfg_tbl_id, &data_tbl_id, &width_cfg_tbl_id, &tbl_idx);
        CTC_DKIT_SENSOR_MAP_LCHIP(lchip, sensor_id);

        /* disable and reset ADC first */
        cmd = DRV_IOR(cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);
        SetTvsenCfg(V, cfgTsenAdcStart_f, &senCfg, 0);
        SetTvsenCfg(V, cfgTsenAdcEn_f, &senCfg, 0);
        cmd = DRV_IOW(cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);
        sal_task_sleep(1);

        cmd = DRV_IOR(cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);
        SetTvsenCfg(V, cfgTsenAdcReset_f, &senCfg, 1);
        cmd = DRV_IOW(cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);
        sal_task_sleep(1);
        SetTvsenCfg(V, cfgTsenAdcReset_f, &senCfg, 0);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);

        /* 1. cfg measure mode, default use single mode */
        cmd = DRV_IOR(cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);
        SetTvsenCfg(V, cfgTsenAdcSingleShotEn_f, &senCfg, 1);
        cmd = DRV_IOW(cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);

        /* 2. cfg measure type, temperature or voltage*/
        cmd = DRV_IOR(cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);
        SetTvsenCfg(V, cfgTsenAdcMode_f, &senCfg, (CTC_DKIT_MONITOR_SENSOR_TEMP == p_sensor->type)?0:1);
        cmd = DRV_IOW(cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);

        /* 3. cfg ADC reset before measurement*/
        cmd = DRV_IOR(cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);
        SetTvsenCfg(V, cfgTsenAdcReset_f, &senCfg, 0);
        cmd = DRV_IOW(cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);

        /* 4. enable ADC*/
        cmd = DRV_IOR(cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);
        SetTvsenCfg(V, cfgTsenAdcEn_f, &senCfg, 1);
        cmd = DRV_IOW(cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);

        /* 5. wait 127920ns */
        sal_task_sleep(1);

        /* 6. cfg measure period */
        cmd = DRV_IOR(width_cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &widthCfg);
        SetTvsenStartPulseWidthCfg(V, cfgTsenAdcStartFirstPulseWidth_f, &widthCfg, 1601184);
        cmd = DRV_IOW(width_cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &widthCfg);

        /* 7. start measurement */
        cmd = DRV_IOR(cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);
        SetTvsenCfg(V, cfgTsenAdcStart_f, &senCfg, 1);
        cmd = DRV_IOW(cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);

        /* 8. wait 16011840ns */
        sal_task_sleep(17);

        /* 9. end measurement */
        cmd = DRV_IOR(cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);
        SetTvsenCfg(V, cfgTsenAdcStart_f, &senCfg, 0);
        cmd = DRV_IOW(cfg_tbl_id, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);

        /* 10. wait 1603680ns */
        sal_task_sleep(2);

        /* 11. read measure result */
        cmd = DRV_IOR(data_tbl_id, DRV_ENTRY_FLAG);
        timeout = 1000;
        do{
            DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senData);
            data_rdy = GetTvsenDataRdy(V, tsenAdcDataReady_f, &senData);
            if (data_rdy)
            {
                measure_result = GetTvsenDataRdy(V, tsenAdcData_f, &senData);
                _sys_at_dkit_sensor_result_proc(lchip, &measure_result, p_sensor->type);
                p_sensor->value[sensor_cnt++] = measure_result;
                break;
            }
            sal_task_sleep(1);
        }while(timeout--);

        for (i = 0; i < 5; i++)
        {
            /* 6. cfg measure period */
            cmd = DRV_IOR(width_cfg_tbl_id, DRV_ENTRY_FLAG);
            DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &widthCfg);
            SetTvsenStartPulseWidthCfg(V, cfgTsenAdcStartNonFirstPulseWidth_f, &widthCfg, 624);
            cmd = DRV_IOW(width_cfg_tbl_id, DRV_ENTRY_FLAG);
            DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &widthCfg);

            /* 7. start measurement */
            cmd = DRV_IOR(cfg_tbl_id, DRV_ENTRY_FLAG);
            DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);
            SetTvsenCfg(V, cfgTsenAdcStart_f, &senCfg, 1);
            cmd = DRV_IOW(cfg_tbl_id, DRV_ENTRY_FLAG);
            DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);

            /* 8. wait 6240ns */
            sal_task_sleep(1);

            /* 9. end measurement */
            cmd = DRV_IOR(cfg_tbl_id, DRV_ENTRY_FLAG);
            DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);
            SetTvsenCfg(V, cfgTsenAdcStart_f, &senCfg, 0);
            cmd = DRV_IOW(cfg_tbl_id, DRV_ENTRY_FLAG);
            DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senCfg);

            /* waiting 8002800ns */
            sal_task_sleep(10);
            cmd = DRV_IOR(data_tbl_id, DRV_ENTRY_FLAG);
            timeout = 1000;
            do{
                DRV_IOCTL(lchip, tbl_idx, DRV_CMD_PP_EN(cmd), &senData);
                data_rdy = GetTvsenDataRdy(V, tsenAdcDataReady_f, &senData);
                if (data_rdy)
                {
                    measure_result = GetTvsenDataRdy(V, tsenAdcData_f, &senData);
                    CTC_DKIT_PRINT_DEBUG("Extra test No.%d, Sensor %u, %6s, raw_data: %u\n", i , sensor_id, (CTC_DKIT_MONITOR_SENSOR_TEMP == p_sensor->type)?"temp":"vol", measure_result);
                    _sys_at_dkit_sensor_result_proc(lchip, &measure_result, p_sensor->type);
                    CTC_DKIT_PRINT_DEBUG("Extra test No.%d, Sensor %u, %6s: %d\n", i , sensor_id, (CTC_DKIT_MONITOR_SENSOR_TEMP == p_sensor->type)?"temp":"vol", CTC_DKIT_SENSOR_VAL_TO_INT32(measure_result));
                    break;
                }
                sal_task_sleep(1);
            }while(timeout--);
            sal_task_sleep(1);
        }
    }

    p_sensor->count = sensor_cnt;

    return CLI_SUCCESS;
}


int32
ctc_at_dkit_monitor_sensor(uint8 lchip, ctc_dkit_monitor_sensor_t type, uint32* p_value)
{
    ctc_dkit_sensor_t chip_sensor;
    uint8 index = 0;

    DKITS_PTR_VALID_CHECK(p_value);
    if (CTC_DKIT_MONITOR_SENSOR_VOL != type && CTC_DKIT_MONITOR_SENSOR_TEMP != type) /*only support get serdes temperature and voltage*/
    {
        return CLI_ERROR;
    }
    sal_memset(&chip_sensor, 0, sizeof(ctc_dkit_sensor_t));
    chip_sensor.type = type;
    /* arctic: 6 temperature sensors per core, 6 voltage sensors per core, get max temperature or min voltage;*/
    sys_at_dkit_get_chip_sensor(lchip, (void*)&chip_sensor);

    *p_value = chip_sensor.value[0];
    for (index = 1; index < chip_sensor.count; index++)
    {
        if (CTC_DKIT_MONITOR_SENSOR_TEMP == type)
        {
            *p_value = (chip_sensor.value[index] >= *p_value)? chip_sensor.value[index] : *p_value;
        }
        if (CTC_DKIT_MONITOR_SENSOR_VOL == type)
        {
            *p_value = (chip_sensor.value[index] <= *p_value)? chip_sensor.value[index] : *p_value;
        }
    }

    return CLI_SUCCESS;
}


int32 ctc_at_dkit_init(uint8 lchip)
{
    uint16 total_que_num = 0;
    uint32 cmd = 0;
    uint8  sensor_id = 0;
    TvsenCfg_m  sen_cfg;

    /* 4. cfg sensor clk div and osr */
    for (sensor_id = 0; sensor_id < 5; sensor_id++)
    {
        cmd = DRV_IOR(TvsenCfg_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, sensor_id, cmd, &sen_cfg);
        SetTvsenCfg(V, cfgTsenAdcClkDiv_f, &sen_cfg, 8);
        SetTvsenCfg(V, cfgTsenAdcOsr_f, &sen_cfg, 3);
        cmd = DRV_IOW(TvsenCfg_t, DRV_ENTRY_FLAG);
        DRV_IOCTL(lchip, sensor_id, cmd, &sen_cfg);
    }
    cmd = DRV_IOR(TvsenCfgTop_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, 0, cmd, &sen_cfg);
    SetTvsenCfgTop(V, cfgTsenAdcClkDiv_f, &sen_cfg, 8);
    SetTvsenCfgTop(V, cfgTsenAdcOsr_f, &sen_cfg, 3);
    cmd = DRV_IOW(TvsenCfgTop_t, DRV_ENTRY_FLAG);
    DRV_IOCTL(lchip, 0, cmd, &sen_cfg);

    /*queue num, AT:912 =52*12 (Network)+128(DMAMc) + 32(DMAUc) + 128(EUNIT) per pp*/
    /* basic channel queue 312(per DP) * 8*/
    total_que_num = CTC_DKIT_PER_DP_CHANNEL_NUM * CTC_DKIT_DP_MAX_NUM * CTC_DKIT_QOS_QUEUE_NUM_PER_CHAN * drv_vchip_get_pp_num(lchip);
    g_usw_dkit_master[lchip]->base_queue_excp = total_que_num;
    /*DMA Queue Mc 128Q*/
    total_que_num += CTC_DKIT_REASON_TOTAL_QUEUE_NUM;
    /*DMA Queue Uc 32Q*/
    total_que_num += CTC_DKIT_REASON_TOTAL_QUEUE_NUM_UC;
    g_usw_dkit_master[lchip]->queue_base_eunit = total_que_num;
    /*Eunit Queue 4(GRP_NUM_EUNIT)*32(GRP_Q_NUM_EUNIT)=128Q*/
    total_que_num += CTC_DKIT_CPU_REASON_GRP_NUM_EUNIT * CTC_DKIT_CPU_REASON_GRP_Q_NUM_EUNIT;
    g_usw_dkit_master[lchip]->queue_num = total_que_num;

    g_dkit_chip_api[lchip]->dkits_get_device_info = ctc_at_dkit_device_info;
    g_dkit_chip_api[lchip]->dkits_get_channel_by_queue = ctc_at_dkit_get_get_channel_by_queue_id;
    g_dkit_chip_api[lchip]->dkits_get_q_depth_igr = ctc_at_dkits_get_q_depth_igr;
    g_dkit_chip_api[lchip]->dkits_get_q_depth_egr = ctc_at_dkits_get_q_depth_egr;
    g_dkit_chip_api[lchip]->dkits_show_q_depth = ctc_at_dkit_show_queue_depth;
    g_dkit_chip_api[lchip]->dkits_show_q_id = ctc_at_dkit_show_queue_id;
    g_dkit_chip_api[lchip]->dkits_dump_serdes_status = ctc_at_dkit_misc_serdes_dump;
    g_dkit_chip_api[lchip]->dkits_serdes_resert = ctc_at_dkit_misc_serdes_reset;
    g_dkit_chip_api[lchip]->dkits_serdes_ctl = ctc_at_dkit_misc_serdes_ctl;
    g_dkit_chip_api[lchip]->dkits_serdes_diag = ctc_at_dkit_misc_serdes_diag; 
    g_dkit_chip_api[lchip]->dkits_read_serdes = ctc_at_dkit_misc_read_serdes;
    g_dkit_chip_api[lchip]->dkits_write_serdes = ctc_at_dkit_misc_write_serdes;
    g_dkit_chip_api[lchip]->dkits_monitor_sensor = ctc_at_dkit_monitor_sensor;
    /*g_dkit_chip_api[lchip]->dkits_show_pcs_status = ctc_tmm_dkit_interface_show_pcs_status;
    g_dkit_chip_api[lchip]->dkits_read_serdes = ctc_tmm_dkit_misc_read_serdes;
    g_dkit_chip_api[lchip]->dkits_write_serdes = ctc_tmm_dkit_misc_write_serdes;
    g_dkit_chip_api[lchip]->dkits_serdes_fw_reg = ctc_tmm_dkit_misc_serdes_fw_reg;
    */return 0;
}


